1. Field of the Invention
The present invention relates to digital circuits and, more specifically to a domino read static random access memory.
2. Description of the Related Art
Static random access memory (SRAM) is a type of volatile digital memory that retains data written to it so long as power is applied to the SRAM. One type of SRAM commonly used in high performance computational circuits is referred to as a “domino-read” SRAM. A domino-read SRAM can have write-though capability that allows a value being written into the SRAM to be read at the output of the SRAM in the same cycle that the value is being written. This feature is useful while performing memory and logic self tests.
When testing integrated circuits, techniques such as ABIST (Array Built In Self Test) and LBIST (Logic Built In Self Test) are used to test memory arrays (such as SRAM arrays) and logic elements. It is desirable to be able test the full latch to latch paths that are used in the chip function at the same frequency that will be used in the system application. If the circuits are tested at a slower frequency or part of the functional path is bypassed, then there could be delay defects that would not be caught by test but result in a failing chip when exercised in the system. This can be an expensive point to find and screen out failing parts.
In some cases, arrays are designed to be latch bounded. There are latches at all the address and data input pins and latches at the data output pins. The array typically would have one clock cycle to perform a read access and have the data captured in the output latch. The data outputs would be launched out of the array on the subsequent cycle. In other cases, arrays do not have an output latch and logic is placed after the array data outputs and downstream capture latches.
ABIST testing of the arrays is straightforward when testing latch bounded arrays. A typical existing non-latch bounded ABIST testing arrangement 10 is shown in FIG. 1. In the case of latch-bounded arrays, ABIST testing will test the entire path and if ABIST is run at system speed, delay defects will be caught. However, for arrays that are not output latch bounded, observation latches can be placed on the outputs so that ABIST testing is straightforward. Unfortunately, ABIST is not testing the full path since the downstream logic is not tested along with the array path. It is important to test the full latch to latch path that includes arrays and logic.
A typical domino read SRAM array is shown in FIG. 2. The SRAM includes a plurality of cells 20 that are each accessed by asserting a word line 14. Each of the SRAM cells 20 includes a pair of cross-coupled inverters 24 that maintain a current state between a pair of isolating transistors 22 that are allowed to conduct if the word line 14 is asserted. Asserting the word line 14 allows the inverters 24 to accept a new data value from a write line 16 (referred to as “WT_B”) or write line WC 18 and to put its data on a BLC bit line 28 and BLT bit line 26.
A local evaluation circuit 40 is used to condition data being written to and read from the SRAM cell 20. The local evaluation circuit 40 (referred to as “LOCAL EVAL”) includes a top half 42 and a bottom half 60, which are reflected copies of each other. (For the sake of simplicity, only the top half 42 is shown in detail herein.) Each half includes circuitry used to precharge a BLC line 26 and BLT line 28 used to write to or read from the SRAM cell 20. The circuitry includes a local precharge line 44 that couples a first PFET 46 to a voltage source and decouples the BLC line 26 when a low voltage is applied thereto, thereby causing the BLC line 26 to be pre-charged when not being accessed. During a write, the local precharge line 44 is raised, thereby decoupling the voltage source at PFET 46 and coupling the BLC line 26 to the write line 16 through NFET 48. This causes PFET 56 to enter into a conducting state (which indicates that a logic “1” is being written to the SRAM 20). On the other hand, if the local precharge line 44 has a high value and if the compliment of the write line 18 (referred to as “WC”) has a high value, then both NFET 52 and NFET 54 will conduct, allowing bit line 28 to begin discharging. Also, when the local precharge line 44 has a low value, a second PFET 50 couples the voltage source to the bit line 28 and prevents the bit line 28 from discharging by turning off a first NFET 52, thereby precharging the bit line 28, resulting in NAND gate 70 turning off NFET 72 when write line 16 has a low value.
Data is read from a precharged DOT line 30. A global precharge signal 34 is coupled to the gate of a PFET 36 so that when the global precharge signal 34 has a low value, the PFET 36 couples the voltage source to the DOT line 30. A charge maintenance circuit 32 may also be employed to maintain a precharged condition of the DOT line 30.
In most cases, a new value being written to the SRAM 20 will appear on the DOT line 30 as it is being written to the SRAM 20, thus giving this circuit its “write-through” capability. In one case, referred to as an “early read” condition, where a “1” is being written to the SRAM 20 to overwrite a “0” currently stored therein, if the “0” driven by SRAM 20 on bit line 28 causes NAND gate 70 to output a “1” before PFET 56 is turned “on” by a “0” placed on write line 16, then NFET 72 will begin to conduct, thereby discharging DOT line 30. This discharge will be impossible to recover from until the next cycle, thereby resulting in an incorrect value being read on the DOT line 30 during the “write-through.”
A global precharge signal 34 is coupled to the gate of a PFET 36 through guaranteed write through circuit 100. PFET 36 selectively precharges the DOT line 30. A charge maintenance circuit 32 may also be employed to maintain a precharged condition of the DOT line 30.
To prevent the DOT line 30 from discharging prematurely during an early read, a guaranteed write through circuit 100 is added to the global precharge line 34. The guaranteed write through circuit 100 ensures that PFET 36 is in a conducting state (i.e., charging DOT line 30) whenever either the global precharge line 34 is in a precharging state or the write line 16 is in a state that would result in a “1” being written to the SRAM 20. In one embodiment, the guaranteed write through circuit 100 includes an AND gate 110 having the global precharge line 34 and the write line 16 as inputs. The output 112 of the AND gate 110 will be a logical “0” when either of these two inputs has a value corresponding to a “0” (which is the case if either precharging is occurring or if a “1” is being written to the SRAM 20). When the output of the AND gate 110 is a “0,” the PFET 36 will couple the DOT line 30 to the voltage source, causing the DOT line 30 to be in a charged state.
This circuit guarantees that a write through will occur on data of both a zero and a one and is selectable. However, using it with certain local evaluation circuits can result in unwanted leakage power. In fact, certain local evaluation circuits can experience an early read without the ability of recovering the bit line 28 completely. This can result in the dot pull down device 72 being turned on partially while the pull up device 36 is held on, resulting in unwanted power dissipation. Additionally, the pull up device 36 on the dot node, even though it presents a small load, it is still on the critical path through the SRAM and, therefore, the power it draws can have affect data integrity.
Therefore, there is a need for an SRAM with a write-through capability that minimizes leakage power dissipation.